IEEE

Efficient Hardware Accelerator Design for AES Encryption Using High-Level Synthesis Techniques

Abstract: In this work, we present the design and implementation of a hardware accelerator for AES encryption and decryption using AMD Vitis HLS and Xilinx Vivado. The primary objective of this work ...
IEEE

A Lightweight Image Encryption Scheme Using Hyperchaotic Map and Collision-Parity Principle

Abstract: An innovative lightweight image encryption scheme with superior security performance has been developed. Initially, we construct a 3-D simple memristive hyperchaotic map (3-D-SMHM) that ...